ALL GATES library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity all is Port ( A : in std_logic; B : in std_logic; not1 : out std_logic; or1 : out std_logic; and1 : out std_logic; nand1 : out std_logic; nor1 : out std_logic; exor1 : out std_logic; exnor1: out std_logic); end all; architecture Behavioral of all is begin not1 <=NOT A; or1 <=A OR B; and1 <=A AND B; nand1 <=A NAND B; nor1 <=A NOR B; exor1 <=A XOR B; exnor1<=not(A XOR B); end Behavioral; HALF ADDER:- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED