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Vhdl codes


                                                ALL GATES

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity all is
    Port ( A : in std_logic;
           B : in std_logic;
           not1  : out std_logic;
           or1   : out std_logic;
           and1  : out std_logic;
           nand1 : out std_logic;
           nor1  : out std_logic;
           exor1 : out std_logic;
           exnor1: out std_logic);
end all;

architecture Behavioral of all is

begin
            not1  <=NOT A;
            or1   <=A OR B;
            and1  <=A AND B;
            nand1 <=A NAND B;
            nor1  <=A NOR B;
            exor1 <=A XOR B;
            exnor1<=not(A XOR B);
           


end Behavioral;












HALF ADDER:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HF is
    Port ( A : in std_logic;
           B : in std_logic;
           CARRY : out std_logic;
           SUM : out std_logic);
end HF;

architecture Behavioral of HF is
begin
             SUM<=A XOR B;
             CARRY<=A AND B;

end Behavioral;



























FU LL ADDER:-


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FA is
    Port ( A : in std_logic;
           B : in std_logic;
           C : in std_logic;
           SUM : out std_logic;
           CARRY : out std_logic);
end FA;

architecture Behavioral of FA is
begin
             SUM<=(A XOR B)  XOR  C;
             CARRY<=(A AND B) OR (B AND C) OR (C AND A);
end Behavioral;





















HALF SUBTRACTOR:-

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity halfsub is
    Port ( A : in std_logic;
           B : in std_logic;
           Diff : out std_logic;
           Borrow : out std_logic);
end halfsub;

architecture Behavioral of halfsub is
begin
             Diff<=A XOR B;
             Borrow<= ((NOT A) AND B);

end Behavioral;


























FULL SUBTRACTOR:-


 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fullsub is
    Port ( A : in std_logic;
           B : in std_logic;
           C : in std_logic;
           DIFF : out std_logic;
           BORROW : out std_logic);
end fullsub;

architecture Behavioral of fullsub is

begin  

            DIFF<=(A XOR B)  XOR C;

            BORROW<=((NOT A) AND B)OR (B AND C) OR ((NOT A) AND C);

end Behavioral;





















                                                4:2 ENCODER

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity enc is
    Port (D : in std_logic_vector(3 downto 0);
   X : out std_logic;
              Y : out std_logic;
               E: in std_logic );
end enc;

architecture Behavioral of enc is
begin
            process(D,E)
begin
            if (E=’0’) then
            X<=’1’;
            Y <=’1’;
Else
            X<=D(2) or  D(3);
            Y <= D(1) or  D(3);

End if;
End process;
end Behavioral;











2:4 DECODER

 library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dec is
    Port ( A : in std_logic;
           B : in std_logic;
            E: in std_logic
           D : out std_logic_vector(3 downto 0));
end dec;

architecture Behavioral of dec is
begin
            process(A,B,E)
begin
            if (E=’0’) then
           
            D<=”0000”;
           
ELSE
             D(0)<=(NOT A) AND  (NOT B);
             D(1)<=(NOT A) AND B;
             D(2)<=A AND (NOT B);
             D(3)<= A AND B;
End if;
End process;
end Behavioral;










4:1 MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity mux i
    Port ( s : in std_logic_vector(1 downto 0);
           d : in std_logic_vector(3 downto 0);
            E : in std_logic
           y : out std_logic);
end mux;

architecture Behavioral of mux is

begin
            process(s,d,E)
            begin
             
            if(E=’0’) then
            y<=’0’;
            else
case s is
            when "00"=> y <= d(0);
            when "01"=> y <= d(1);
            when "10"=> y <= d(2);
            when "11"=> y <= d(3);
            when others => null;
            end case;
            end if;
            end process;

end Behavioral;












                                                1:4 DEMUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity demux i
    Port ( s : in std_logic_vector(1 downto 0);
           d : out std_logic_vector(3 downto 0);
            E : in std_logic
           y : in std_logic);
end demux;

architecture Behavioral of demux is

begin
            process(s,y,E)
            begin
             
            if(E=’0’) then
            d<=”0000”;
            else
case s is
            when "00"=> d(0)<= y;
            when "01"=> d(1)<= y;
            when "10"=> d(2)<= y;
            when "11"=> d(3)<= y;
            when others => null;
            end case;
            end process;

end Behavioral;













                                                COMPARATOR
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comp is
    Port ( a : in std_logic_vector(2 downto 0);
           b : in std_logic_vector(2 downto 0);
           alb : out std_logic;
           agb : out std_logic;
           aeb : out std_logic);
end comp;

architecture Behavioral of comp is
begin
            process(a,b)
            begin
           
if (a<b) then alb<='1';
            else alb<='0';
            end if ;
           
if (a>b) then agb<='1';
            else agb<='0';
            end if  ;

            if (a=b) then aeb<='1';
            else aeb<='0';
            end if;
            end process;
end Behavioral;

















                                    BINARY TO GRAY CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity BG is
    Port ( B : in std_logic_vector(3 downto 0);
           G : out std_logic_vector(3 downto 0));
end BG;

architecture Behavioral of BG is

begin
    G(0)<= B(1)XOR B(0);
    G(1)<= B(2) XOR B(1);
    G(2)<= B(3) XOR B(2);
    G(3)<= B(3);

end Behavioral;























                                              2- BIT ALU
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity alu is
    Port ( a : in std_logic_vector(1 downto 0);
           b : in std_logic_vector(1 downto 0);
           sel : in std_logic_vector(1 downto 0);
           enb : in std_logic;
           op : out std_logic_vector(1 downto 0));
end alu;

architecture Behavioral of alu is

begin
            process(a,b,sel,enb)
           
            begin
           
            if (enb='1')  then
            case sel is
                        when"00"=>op<=a+b;
                        when"01"=>op<=a-b;
                        when"10"=>op<=a or b;
                        when"11"=>op<=a and b;
                        when others=> null;
            end case;
           
            else
            out<="00";
            end if;
            end process;
end Behavioral;










                                                D- FLIP FLOP

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ff is
    Port ( d   : in std_logic;
           clk : in std_logic;
           re  : in std_logic;
           q   : inout std_logic;
         Qb  : out std_logic);
end ff;
architecture Behavioral of ff is
begin
            process(clk,re)
           
begin
            if (re='1')then
            q<='0';
           
elsif (clk='1'and clk'event) then
            q<=d;
            end if;
Qb<=not q;

            end process;
           

end Behavioral;
















T- FLIP FLOP


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity tf is
    Port ( clk : in std_logic;
           t : in std_logic;
           re  : in std_logic;
           q : inout std_logic;
           Qb : out std_logic);
end tf;

architecture Behavioral of tf is
begin
            process(clk,re)
            begin
           
           
begin
            if (re='1')then
            q<='0';
           
elsif (clk='1'and clk'event) then
            q<=not t;
            end if;
            end process;
            Qb<=not q;


end Behavioral;












SR- FLIP FLOP


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sr is
    Port ( s : in std_logic;
           r : in std_logic;
           re : in std_logic;
           clk : in std_logic;
           q : inout std_logic;
           Qb : out std_logic);
end sr;
architecture Behavioral of sr is

begin
            process(clk, re)
           
            begin
            if(re='1')then
             q<='0';
            elsif(clk='1'and clk'event)then
           
            if(s='0' and r='0') then             q<='0';
           elsif(s='0' and r='1') then          q<='0';
           elsif(s='1' and r='0') then          q<='1';
           elsif(s='1' and r='1') then          q<='0';
            end if;
            end if;
           
            end process;

            Qb<= not q;
end Behavioral;









JK- FLIP FLOP

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity jkf is
    Port ( j : in std_logic;
           k : in std_logic;
           re: in std_logic;
           mclk : in std_logic;
           q : inout std_logic;
           Qb : out std_logic);
end jkf;

architecture Behavioral of jkf is
             SIGNAL MCLKDIV:std_logic_vector( 25 downto 0);
             SIGNAL clk : std_logic;
begin
            process(clk, re)
            begin
            if(re='1')then
 q<='0';
            elsif(clk='1'and clk' event) then
if(j='0' and k='0') then             q<='0';
            elsif(j='0' and k='1') then        q<='0';
            elsif(j='1' and k='0') then        q<='1';
            elsif(j='1' and k='1') then        q<=not q;
            end if;     
            end if;
            Qb<= not q;
            end process;

             process(mclk, re)
             begin
            if(mclk='1'and mclk' event) then
             MCLKDIV<=MCLKDIV+1;
             END IF;
             clk<=MCLKDIV(20);
             END PROCESS;
end Behavioral;



          BINARY UP COUNTER

          library IEEE;
          use IEEE.STD_LOGIC_1164.ALL;
          use IEEE.STD_LOGIC_ARITH.ALL;
          use IEEE.STD_LOGIC_UNSIGNED.ALL;

          entity BC is
           Port ( MCLK : in std_logic;
           RE : in std_logic;
           Q : INOUT std_logic_vector(3 downto 0));
           end BC;

           architecture Behavioral of BC is
             SIGNAL TEMP:std_logic_vector( 3 downto 0);
             SIGNAL MCLKDIV:std_logic_vector( 25 downto 0);
             SIGNAL CLK : std_logic;
           begin
             PROCESS(CLK)
             BEGIN
             IF (RE='1') THEN
             TEMP<="0000";
             ELSIF(CLK'EVENT AND CLK='1') THEN
             TEMP<=TEMP+1;
            END IF;
            Q<=TEMP;
             END PROCESS;
           
             PROCESS(MCLK)
             BEGIN
             IF(MCLK'EVENT AND MCLK='1') THEN
             MCLKDIV<=MCLKDIV+1;
             END IF;
             CLK<=MCLKDIV(20);
             END PROCESS;

           end Behavioral;









          JOHNSON COUNTER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JHN is
    GENERIC(WIDTH:POSITIVE:=4);
    Port ( MCLK : in std_logic;
           CLR : in std_logic;
           Q : BUFFER std_logic_vector(WIDTH-1 downto 0));
end JHN;

architecture Behavioral of JHN is
            SIGNAL MCLKDIV:std_logic_vector( 25 downto 0);
            SIGNAL CLK : std_logic;
begin
             PROCESS(CLK)
             BEGIN
             IF(CLK'EVENT AND CLK='1') THEN
              IF CLR='0' THEN
              Q<=(OTHERS=>'0');
              ELSE
             Q(WIDTH-1 downto 0)<=(NOT Q(0))&Q(WIDTH-1 downto 1);
             END IF;
             END IF;
             END PROCESS;
           
             PROCESS(MCLK)
             BEGIN
             IF(MCLK'EVENT AND MCLK='1') THEN
             MCLKDIV<=MCLKDIV+1;
             END IF;
             CLK<=MCLKDIV(20);
             END PROCESS;
end Behavioral;








                                  BCD COUNTER

          library IEEE;
          use IEEE.STD_LOGIC_1164.ALL;
          use IEEE.STD_LOGIC_ARITH.ALL;
          use IEEE.STD_LOGIC_UNSIGNED.ALL;

          entity BC is
           Port ( MCLK : in std_logic;
           RE : in std_logic;
           Q : INOUT std_logic_vector(3 downto 0));
           end BC;

           architecture Behavioral of BC is
             SIGNAL TEMP:std_logic_vector( 3 downto 0);
             SIGNAL MCLKDIV:std_logic_vector( 25 downto 0);
             SIGNAL CLK : std_logic;
           begin
             PROCESS(CLK)
             BEGIN
             IF (RE='1') THEN
             TEMP<="0000";
             ELSIF(CLK'EVENT AND CLK='1') THEN
             TEMP<=TEMP+1;
            IF (TEMP=”1001”) THEN
            TEMP<= “0000”;
             END IF;
            END IF;
            Q<=TEMP;
             END PROCESS;
           
             PROCESS(MCLK)
             BEGIN
             IF(MCLK'EVENT AND MCLK='1') THEN
             MCLKDIV<=MCLKDIV+1;
             END IF;
             CLK<=MCLKDIV(20);
             END PROCESS;

           end Behavioral;






 BCD TO SEVEN SEGMENT DISPLAY

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity BCD is
    Port ( COUNT : in std_logic_vector(3 downto 0);
           SOUT : out std_logic_vector(6 downto 0));
end BCD;

architecture Behavioral of BCD is

begin
                       
           
            PROCESS(COUNT)
            BEGIN
             CASE COUNT IS
             WHEN "0000"=>SOUT<="1111110"; --SEG-A-43
             WHEN "0001"=>SOUT<="0110000"; --SEG-B-44
             WHEN "0010"=>SOUT<="1101101"; --SEG-C-45
             WHEN "0011"=>SOUT<="1111001"; --SEG-D-46

             WHEN "0100"=>SOUT<="0110011"; --SEG-E-47
             WHEN "0101"=>SOUT<="1011011"; --SEG-F-50
             WHEN "0110"=>SOUT<="1011111"; --SEG-G-48
             WHEN "0111"=>SOUT<="1110000";        
             WHEN "1000"=>SOUT<="1111111";

             WHEN OTHERS=>SOUT<="1110011";

END CASE;
END PROCESS;


end Behavioral;



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