ALL GATES library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity all is Port ( A : in std_logic; B : in std_logic; not1 : out std_logic; or1 : out std_logic; and1 : out std_logic; nand1 : out std_logic; nor1 : out std_logic; exor1 : out std_logic; ...